#   Copyright 2016 Robert Elder Software Inc.
#   
#   Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in 
#   compliance with the License.  You may obtain a copy of the License at
#   
#       http://www.apache.org/licenses/LICENSE-2.0
#   
#   Unless required by applicable law or agreed to in writing, software distributed under the License is 
#   distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 
#    See the License for the specific language governing permissions and limitations under the License.

                                                     One-Page CPU

+-----------------+<--------+----32-bits----------------->+--------------------------------------------------+
|                 |<5-bits >|<----------27-bits---------->|                                                  |
|    Assembly     |  Ctrl   |          Data Layout        |                  Description                     |
+-----------------+---------+-----------------------------+--------------------------------------------------+
| add rX rY rZ    |  00000  | XXXXXXXXXYYYYYYYYYZZZZZZZZZ | rX = rY + rZ (32-bit unsigned)                   |
| sub rX rY rZ    |  00001  | XXXXXXXXXYYYYYYYYYZZZZZZZZZ | rX = rY - rZ (32-bit unsigned)                   |
| mul rX rY rZ    |  00010  | XXXXXXXXXYYYYYYYYYZZZZZZZZZ | rX = rY * rZ (32-bit unsigned) Low 32 bit result |
| div rX rY rZ    |  00011  | XXXXXXXXXYYYYYYYYYZZZZZZZZZ | rX = rY / rZ (32-bit unsigned) See DIV_ZERO flag |
| and rX rY rZ    |  00100  | XXXXXXXXXYYYYYYYYYZZZZZZZZZ | rX = rY & rZ (bitwise logical and)               |
| or rX rY rZ     |  00101  | XXXXXXXXXYYYYYYYYYZZZZZZZZZ | rX = rY | rZ (bitwise logical or)                |
| not rX rY       |  00110  | XXXXXXXXXYYYYYYYYY--------- | rX = ~rY (bitwise logical not)                   |
| loa rX rY       |  00111  | XXXXXXXXXYYYYYYYYY--------- | Load contents of memory location rY into rX      |
| sto rX rY       |  01000  | XXXXXXXXXYYYYYYYYY--------- | Store contents of rY at memory location in rX    |
| shr rX rY       |  01001  | XXXXXXXXXYYYYYYYYY--------- | rX = (rX logical shift rY bits to the right)     |
| shl rX rY       |  01010  | XXXXXXXXXYYYYYYYYY--------- | rX = (rX logical shift rY bits to the left)      |
| beq rX rY i     |  01011  | XXXXXXXXXYYYYYYYYYiiiiiiiii | PC = PC + i * 4 if rX == rY (i is 9-bit signed)  |
| blt rX rY i     |  01100  | XXXXXXXXXYYYYYYYYYiiiiiiiii | PC = PC + i * 4 if rX < rY (i is 9-bit signed)   |
| ll rX 0xN       |  01101  | XXXXXXXXX--NNNNNNNNNNNNNNNN | load literal 16 bits into rX; high bits set to 0 |
+-----------------+---------+-----------------------------+--------------------------------------------------+
| Registers Overview                                                                                         |
|                                                                                                            |
| #0) PC (Program Counter) Points to next instruction.           #3) ZR (Zero Register)  Initialized to 0.   |
| #1) SP (Stack Pointer)   Points to the top item on the stack.  #4) FR (Flags Register) Special CPU flags.  |
| #2) FP (Frame Pointer)   Points to previous frame pointer.     #5) WR (Word Register)  Initialized to 4.   |
|                                                                                                            |
| At CPU startup, WR = 0x4, FR = 0x200.  All other registers are initialized to 0.                           |
| Special registers #0 to #5 are PC, SP, FP, ZR, FR, WR.  General registers #6 to #511 are named r1 to r506. |
+------------------------------------------------------------------------------------------------------------+
| Flags Register (FR) Description                                                                            |
|                                                                                                            |
| Bit 0:     Writing one to this bit halts the processor.  No further instructions or interrupts execute.    |
| Bit 1:     Global Interrupt Enable.  All interrupts enabled when 1.  All interrupts disabled otherwise.    |
| Bit 2:     When set to 1, atomically sets bit 1 of FR to 1; bit 2 of FR to 0; PC to [SP]; SP to SP + WR.   |
| Bit 3:     TIMER1 interrupt enable.  See TIMER1_PERIOD.                                                    |
| Bit 4:     TIMER1 interrupt asserted.  CPU sets to 1.  User must set to 0.                                 |
| Bit 5:     UART1_OUT interrupt enable.  Used for detecting when bit 9 of FR has been set by CPU.           |
| Bit 6:     UART1_OUT interrupt asserted.  CPU sets to 1.  User must set to 0.                              |
| Bit 7:     UART1_IN interrupt enable.  Used for detecting when bit 10 of FR has been set by CPU.           |
| Bit 8:     UART1_IN interrupt asserted.  CPU sets to 1.  User must set to 0.                               |
| Bit 9:     UART1_OUT ready.  Indicates if UART1_OUT is ready.  CPU sets to 1.  User must set 0.            |
| Bit 10:    UART1_IN ready.  Indicates if UART1_IN contains input data.  CPU sets to 1.  User must set 0.   |
| Bit 11:    DIV_ZERO interrupt asserted due to a division by 0.  CPU sets to 1.  User must set to 0.        |
| Bit 12:    PAGE_FAULT_EXCEPTION interrupt asserted.  CPU sets to 1.  User must set to 0.                   |
| Bit 13:    PAGE_FAULT_EXCEPTION interrupt enabled.  Enables or disables paging.  Ignores FR bit 1 state.   |
| Bit 14-31  Unused.                                                                                         |
| Handling an interrupt atomically sets bit 1 of FR to 0; SP to SP - WR; [SP] to PC; then PC to IRQ_HANDLER  |
+------------------------------------------------------------------------------------------------------------+
| Memory Overview                                                                                            |
|                                                                                                            |
| 0x300000 UART1_OUT          After bytes located here are read by peripheral, CPU sets bit 9 of FR to 1.    |
| 0x300010 UART1_IN           Input from peripheral is stored at this address, CPU sets bit 10 of FR to 1.   |
| 0x300020 IRQ_HANDLER        The 4 byte address of the global interrupt handler function.                   |
| 0x300030 TIMER1_PERIOD      Assert bit 4 of FR when (# instructions executed) mod TIMER1_PERIOD == 0       |
| 0x300040 PAGE_POINTER       A pointer to the current level 2 page table.                                   |
| 0x300044 PFE_PAGE_POINTER   A pointer to the level 2 page table most recently involved in a page fault.    |
| 0x300048 PFE_PC_VALUE       The program counter during the most recent page fault.                         |
| 0x30004C PFE_ACCESS         The access level being requested during the most recent page fault.            |
| 0x300050 PFE_VIRTUAL        The virtual address being accessed during the most recent page fault.          |
|                                                                                                            |
| All memory mapped registers are 4 bytes, and initialized to 0 at startup, other memory locations are       |
| initialized to an unspecified value.  Out of memory, or non 4 byte aligned access asserts bit 0 of FR.     |
+--------------------------+<-----------------------------32-bits-------------------------->+----------------+
| Paging (PT = Page Table) |<--------11 bits------->|<-------11 bits-------->|<--10 bits-->| I = Initialized |
|        Virtual Address:  | lvl 2 PT entry index   | lvl 1 PT entry index   | Byte Offset | R = Read        |
|        Level 2 PT Entry: | High 22 bits of address of lvl 1 PT             | I---------  | W = Write       |
|        Level 1 PT Entry: | High 22 bits of linear page address in memory   | I------RWX  | X = Execute     |
+--------------------------+-------------------------------------------------+-------------+-----------------+
The sha1sum of the lines above is 3b458c43daa718d2c8d4e6185afe03ddcdda0bfb